1. Technical Field
The present invention relates to a test apparatus and a test method. More particularly, the present invention relates to a test apparatus and a test method for testing a memory under test.
2. Related Art
A memory test apparatus is configured to generate an address signal and a data signal at a pattern generator and apply the generated address and data signals to a memory under test to perform data writing. The memory test apparatus also generates an expected value signal in association with the address signal at the pattern generator, and compares an output signal read from the memory under test with the expected value signal. When the output signal does not match the expected value signal, the memory test apparatus stores fail data representing the mismatch in an address fail memory (AFM) in a defect analysis memory in association with the address indicated by the address signal. The memory test apparatus performs a defect repair analysis on the memory under test by referring to the fail data stored in the AFM (see, for example, Japanese Patent Application Publication No. 10-055694).
FIG. 7 illustrates the temporal relation between memory tests and defect repair analyses in the conventional art. To begin with, a conventional memory test apparatus clears an AFM by setting the logical values of all the pieces of data stored therein at zero (0). Subsequently, the memory test apparatus tests a memory under test and stores fail data by setting the logical value of corresponding data at one (1), if any defects are detected as the test proceeds. On completion of the test on the memory under test, the memory test apparatus performs a defect repair analysis on the memory under test by referring to the fail data stored in the AFM. After this, the memory test apparatus clears the AFM by setting the logical values of the pieces of data stored therein at 0 and then starts a test on a next memory under test.
Japanese Patent Application Publication No. 2005-259265 discloses a memory testing technique without the need of the above-mentioned AFM clearing step. A memory test apparatus employing this technique includes a clear mark memory (CMM) that retains, in association with each of the addresses of a memory under test, information indicating whether the associated address is to be tested for the first time. The memory test apparatus judges whether each address is to be tested for the first time by referring to the CMM. If a given address is to be tested for the first time, the memory test apparatus overwrites the old fail data in the AFM with the new fail data. If the given address is to be tested for the second or further time, the memory test apparatus stores the new fail data into the AFM in a read-modify-write manner. After completing the test on the memory under test, the memory test apparatus clears the CMM and then starts a next memory test.
Here, AFMs have a similar capacity as memories under test, and a recent exponential increase in the capacity of the memories under test thus results in a dramatic increase in the capacity of the AFMs. Such an increase inevitably increases the time required to clear the AFMs. Here, to remove the need to clear the AFMs, CMMs may be provided. However, the capacity of the CMMs is in proportion to the capacity of the AFMs, which also means a longer time required to clear the CMM. The memory test apparatus is required to discontinue the tests and wait for a long period of time to clear the AFMs or CMMs, thereby suffering from a lower testing throughput.